COMPASS 2024 - Tokyo, Japan

About COMPASS 

This Year's COMPASS Theme is Megatrends in Test and Measurement

FormFactor’s COMPASS test and measurement community event brings together FormFactor customers from around the
world to discuss the products and technologies shaping our future. Industry leaders and speakers from corporations,
leading-edge research institutions and FormFactor share test insights on a wide variety of emerging applications
including 5G, trends in advanced packages, next generation memories and other devices, ultra-low noise testing,
cryogenic probing and millimeter-wave measurement and calibration.

tokyo

2024年2月28日(水)

場所:鉃鋼エグゼクティブラウンジ&カンファレンスルーム

東京都千代田区丸の内1-8-2 鉄鋼ビルディング南館4階

セミナー開催時間: 11:00~16:30 (10:30 受付開始)
16:45~18:30レセプション

参加費用:無料

Agenda

セミナータイトルをクリックすると要旨がご覧になれます

English titles and descriptions are available by expanding each item.

Welcome & Reception

Mike Slessor, President & CEO - FormFactor Inc.

代表取締役 川又 信尋
Nobuhiro Kawamata, , FormFactor Inc.

Kainoa Kekahuna, Applications Engineering Manager, FormFactor Inc.

人為的なミスを無くし、再現性のあるキャリブレーション結果を保証し、大幅な時間の削減を実現する、FormFactor最新のSiPhカップリング・テクノロジーであるPharosプローブと最新制御ソフトウェアが提供する、”Four-Mouse-Click”(マウスを4回クリックするだけの自動キャリブレーション)についてご紹介します。
 
Pharos Vertical and Edge Coupling Low Loss SiPh Wafer Test with Fully Automated Calibration - From Probe Install to Successful V-groove Wafer Level Test in 90 Minutes
 
In this talk we will discuss FormFactor’s industry leading silicon photonics coupling technology, Pharos, for edge coupling in V grooves and lowest loss coupling on grating couplers. Further we will cover the new four mouse-click automated calibration routine released in the latest silicon photonics software solution suite.
 
FormFactor’s SiPh solution includes a built-in power measuring function that quantifies the laser output coming directly from one of the Pharos fiber channels. This allows the user the flexibility to move from measurements directly on the wafer to an aux site and verify the laser power coming out of the probes, automatically position one of the eight channels of the probes, and to go back to the last die or subdie measured to proceed. All that is accomplished by sending one integrated command, without the need to manually navigate to the right spot on the aux site, position the probe in the correct location, and so on. This eliminates user miscues completely and is a great timesaver.
 
Also, with a four mouse-click automated calibration, manual errors are eliminated. This automated routine assures consistent and repeatable calibration results without missing a step, and saves significant time.
 

Lunch Break

量子コンピュータとその低温基盤
 
量子コンピュータという言葉を最近よく耳にしますが、まだ馴染みのない分野です。本プレゼンテーションでは基本レベルでの量子コンピューティングとは何か、主要なアプリケーションのいくつか、および量子コンピューティングの基盤技術のいくつかについて概説し、特に低温技術に焦点を当てます。
 
Quantum Computing and it's Cryogenic Underpinnings
 
Mike Snow, Director of Engineering, FormFactor, Inc.

Quantum control chips are required to be operated at cryogenic temperature to realize large-scale quantum computers. This presentation will introduce a design example of cryogenic analog circuit for controlling silicon spin qubits and its measurement results at 4 K temperature. The presentation will also provide cryogenic evaluation results of a multi-chip packaging structure for qubit installation at 100 mK temperature.

神戸大学
大学院 科学技術イノベーション研究科
准教授 博士(工学)
三木 拓司 様

多数の量子ビットを集積した大規模量子コンピュータを実現するためには、量子ビット制御回路の極低温動作が不可欠です。本プレゼンテーションでは、シリコンスピン量子ビットを制御するための極低温アナログ回路の設計事例と4Kでの測定結果を紹介します。また、量子ビットチップを積層するマルチチップ構造の100mKにおける極低温耐性評価についてもご紹介します。

Cryogenic Measurements of Quantum Control Chips for Large-scale Silicon Quantum Computers

Takuji Miki - Associate Professor, Graduate School of Science, Technology and Innovation Department of Science, Technology and Innovation - Kobe University

Quantum control chips are required to be operated at cryogenic temperature to realize large-scale quantum computers. This presentation will introduce a design example of cryogenic analog circuit for controlling silicon spin qubits and its measurement results at 4 K temperature. The presentation will also provide cryogenic evaluation results of a multi-chip packaging structure for qubit installation at 100 mK temperature.

COFFEE BREAK & EXHIBITION

東京工業大学
科学技術創生研究院 未来産業技術研究所
特任教授 博士(工学)
栗田 洋一郎 様

随時更新予定

Latest Trends in Chiplet Integration Technology

Kurita Yoichiro - Specially Appointed Professor, Laboratory for Future Interdisciplinary Reserch of Science and Technology (FIRST), Institute of Innovative Reserach - Tokyo Institute of Technology

Abstract Not Available

フォームファクター株式会社
シニアディレクター
佐伯 多加夫

半導体業界がポスト・ムーアの法則の時代に進む中、アドバンスト・パッケージングは、コストの削減と同時にパフォーマンス、コンピューティング能力、周波数帯域幅の向上を必要とする次世代デバイスを実現するテクノロジーとして注目されています。 2.5D および 3D IC パッケージング技術は、ますます多くのアプリケーションに利用されています。 こうした性能要件の高まりにより、実行可能なコストでデバイスの性能と歩留まりを確保するために、新たなテストの課題が増え続けています。 これらの要件をサポートするために、テスト戦略とソリューションは進化しています。 本プレゼンテーションでは、先進的なパッケージング オプション、特に 2D および 3D IC テクノロジーの現在の傾向を、プローブ カードの観点からのテスト要件と、現在および次世代のデバイス テストに適合するプローブ カード ソリューションとともにレビューします。

Emerging Trends, Challenges and Solutions for Probing Next Generation Advanced Packaging Devices

Saeki Takao - Sr Director, Manufacturing Engineering - FormFactor Inc.

As the semiconductor industry continues into the post Moore’s Law era, Advanced Packaging continues to emerge as an enabling technology for next generation devices that require increased performance, computing power and bandwidth all while driving lower costs. 2.5D and 3D IC packaging technology is being utilized for ever increasing applications. These increased performance requirements are driving new and ever-increasing test challenges in order to insure device performance and yield with commercially viable costs. Test strategies and solutions are evolving in order to support these requirements. This presentation will review the current trends in advance packaging options, particularly 2D and 3D IC technology along with the test requirements from a probe card perspective and probe card solutions to meet the current and next generation device testing.

COFFEE BREAK & EXHIBITION

日本テキサスインスツルメンツ合同会社
美浦工場
安藤 剛樹 様

Parametric Test - Outline for Parametric Test-

Takeki Andoh - Parametric Test Engineer, Texas Instruments Japan Limited

Provides an overview of parametric testing. Parametric testing consists of all the elements and wiring of an integrated circuit as a single unit.
It is a process to determine whether each element is completed according to the design by measuring the characteristics of each element. Because test elements are formed through a variety of processes, Also this is a very important test process that supports manufacturing equipment quality in each process.
In this presentation, we will deepen our understanding of what parametric testing should be like.

 

Jerry Broz, Sr. VP of Business Development & Strategic Marketing, Delphon Industries, LLC.

すべての電気テストは、高度なプローブ カードを使用してデバイス上で物理的な「タッチダウン」によって実行されます。
ウェハテストレベルでの要求に対し、テストセルツール/革新的なプローブカード/新材料の開発が必須です。
テストの複雑さが増す中で、高度なプローブ洗浄戦略は、歩留まりを最大化するための基礎となります。

本プレゼンテーションでは、プローブ カードのクリーニングの プロセスとそのイノベーション、コラボレーション、パートナーシップ、および学際的な問題解決アプローチを必要とするさまざまな技術的 (および商業的) 課題に焦点を当てます。

Address Data Integrity Challenges During Expanded Wafer Test

Expenditures associated with development, design, and fabrication of monolithic semiconductors with leading-edge processes have escalated to over 70-80% of the total cost of the device. Various IP integration strategies combine advantages of multiple processors, sensors, RF, and memory modules, among others, to meet consumer demands for enhanced performance, reduced size, weight, and power consumption at a lower overall cost. A worst-case cost scenario within these systems is a single failure, and this sets-the-stage for test complexity requirements combined with the highest levels data quality and data integrity. As a result, IDMs and foundries will rely even more heavily on test coverage thoroughness before integration and advanced packaging to validate “good enough” semiconductor IP.
 
All electrical testing is performed with physical “touchdowns” on the wafer or device under test using advanced probe cards. Developments in test-cell tooling, innovative probe-cards, and new materials are needed to meet challenges when addressing wafer-level-test requirements and facilitating expanded, or “shift left” test methodologies, for economically identifying device failures. Cost-effective probe cleaning strategies are foundational to assure data quality and maximize stable first pass yields with increasing test complexity. This presentation will discuss probe card cleaning processes and highlight the various technical (and commercial) challenges that require innovation, collaboration, partnerships, and an interdisciplinary problem-solving approach. Deep materials knowledge and collaborative innovation is integral for developing the cleaning materials required for maintaining contact reliability during advanced wafer-level test.

Event closure

End of event reception

時間や内容は予告なく変更する場合がございます

Meet the Speakers

headshot_mike

Mike Slessor
President & CEO

headshot_nobuhiro_kawamata

代表取締役 川又 信尋

headshot_kainoa_kekahuna

Kainoa Kekahuna
Applications Engineering Manager
FormFactor, Inc.

headshot_takuji_miki

神戸大学
大学院 科学技術イノベーション研究科
准教授 博士(工学)
三木 拓司 様

headshot_mike_snow

Mike Snow
Director of Engineering
FormFactor, Inc.

headshot_kurita_yoichiro
東京工業大学
科学技術創生研究院 未来産業技術研究所
特任教授 博士(工学)
栗田 洋一郎 様
headshot_takao_saeki

フォームファクター株式会社
シニアディレクター
佐伯 多加夫

headshot_jerry_broz
Jerry Broz
VP Business Development & Strategic Marketing
Delphon Industries, LLC.
takeki-andoh
日本テキサスインスツルメンツ合同会社
美浦工場
安藤 剛樹 様

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COMPASS 2024 - Japan
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