イントロダクション

Mike Slessor, President & CEO - FormFactor Inc.

代表取締役　川又　信尋
Nobuhiro Kawamata, FormFactor Inc.

高度なヘテロジニアス・インテグレーションの新たなレベルの革新

Takashi Kariya, Corporate Vice President / Head of Lab, Device Solutions R&D Japan Advanced Package Lab, Samsung Japan Corporation

近年、デバイスメーカーが将来の革新性を追求しようとした時、ヘテロジニアスパッケージによる優位性が必要となっています。

新たなハイエンドコンピューティング、メモリ、モバイルアプリケーションを実現するための技術ロードマップ、課題と機会の観点からサムスンAVPプラットフォームをご紹介します。

Advances in heterogeneous chip packages are needed to empower today’s device manufacturers to pursue tomorrow’s breakthroughs. Samsung AVP Platform is to be introduced in terms of technology roadmap, challenges and opportunities for emerging high-end computing, memory and mobile applications.

昼食 ※ご希望の方には昼食をご用意させていただきます

先端SoCデバイスおよびアプリケーションのためのウェハプローブテストの課題と解決策

Cameron Harker, Sr. Director, Business Development, FormFactor Inc.

As advanced technology nodes make it more difficult to maintain Moore’s Law, semiconductor manufactures need to find solutions to enable increased transistor density, develop larger devices and reduce device costs.  Next generation device test requirements are also demanding higher speeds and a significant increase in bump count leading to increasing probe card complexity including higher and higher pin counts. 

To meet these challenges, advanced devices and applications are utilizing advanced packing technologies to address the industry drivers for technology and reduced costs.  Advanced packaging technologies help reach the next generation device requirements but introduce new challenges for testing devices that utilized Advanced Packaging. 

This presentation will review some of the most recent SoC device test trends including  Advanced Packaging trends and wafer test challenges along with unique probe solutions from FormFactor.

低ノイズ環境に向けての電流ノイズの重要性

Masahiro Sameshima, Senior Staff Application Engineer, FormFactor Japan

低ノイズ環境に向けての電流ノイズの重要性

The noise issues that began to emerge around 2010 in wafer prober systems and measurement environments for research and development were largely resolved by addressing the major noise problems by around 2015. In this discussion, I will explain the methods used to assess the noise levels in the measurement environment and identify the main sources of noise.

2010年頃から研究開発のためのウェハプローバーシステムおよび測定環境で発生し始めたノイズの問題は、2015年頃までに主要なノイズ問題に対処することでほぼ解決されました。この議論では、測定環境におけるノイズレベルを評価し、主なノイズ源を特定するために使用された方法について説明します。

AI/HPC向けChipletに対応するテスト戦略の最適化

Optimization of Test Strategies for Innovative Chiplets for AI/HPC Applications

コーヒーブレイク/エキシビジョン

シリコンフォトニクスの生産における技術の進化

Divya Pratap, Silicon Photonics Program Director, FormFactor Inc.

With growth in foundries ecosystem and maturity in passive and active photonic devices, silicon photonics testing is rapidly moving into production environment. Wafer-level testing is crucial during the development phase, where frequent tests enable design revisions and performance optimization. However, the shift from development to production poses significant challenges.

This talk will discuss strategies and techniques to ensure exceptional reliability from wafer probing systems including how to maintain consistent operation under high pressure but also address scalability, throughput, and robustness to achieve efficiency and reliability in production environments.

FormFactor の次世代 DRAM テクノロジー向けプローブ ソリューション

David Cooke, Sr. Product Marketing Manager, FormFactor, Inc.

Kevin Tran, Senior Director of Product Marketing, FormFactor Inc.

Smaller DRAM geometries, advanced packaging, and higher interface speeds are driving demand for new and more robust testing capabilities. A comprehensive test approach is mandatory to ensure the highest level of quality, reliability, and performance of the DRAM devices. In this talk, FormFactor will present its probe card technology, specifically designed to enable DRAM manufacturers to enhance test coverage, optimize yield, and accelerate mass production ramps.

コーヒーブレイク/エキシビジョン

AI/HPC向けChipletに対応するテスト戦略の最適化

Shinji Fujita, Principal/ Test Strategist, Advantest

Generative AI/HPCカテゴリに代表されるChiplet等、実装技術の進化等、半導体業界の様々な技術革新に伴い、テスト工程にも大きな変革、最適化が求められています。

特にChiplet半導体製品に代表される歩留まり向上、品質保証の難易度が上がる中で、Wafer-SortやFinal-Testに加えて新たなDie-Level Testのアプローチや、Shift-LeftなのかShift-Rightなのか? テスト戦略の更なる最適化に向けて、テスタメーカーの観点から、今後の重要課題についての見解を述べます。

Along with various technological innovations in the semiconductor industry, advanced packaging technology such as Chiplets represented by the Generative AI/HPC category, major changes and optimization are required also in the test process.

As the difficulty of yield improvement and quality assurance increases, in addition to Wafer-Sort and Final-Test, we are also introducing new Die-Level Test initiatives. Is it Shift-Left or Shift-Right?  We will provide important insights from the perspective of tester manufacturers in order to further optimize test strategies.

高ボリュームテストのOEE最大化: 革新的なプローブクリーニングおよびデバイストランスポートソリューション

Dr. Jerry Broz, VP of Business Development & Strategic Marketing, Delphon Industries, Inc.

The costs associated with building monolithic, advanced node monolithic semiconductors account for 70-80% of device costs. Integrating processors, sensors, RF, and memory modules enhances performance and reduces costs. A single failure can be expensive, necessitating complex testing to ensure data quality and integrity. Testing singulated die and chiplets ensures known-good-die and aligns test parameters with packaged parts. Electrical testing involves physical "touchdowns" using advanced probe card technologies, which create contamination over time. MEMS-based probes have led to engineered cleaning materials, with in-situ techniques addressing CRES instability and debris removal, maintaining throughput. Even a 0.5% improvement in OEE is significant in high-volume production.

Advancements in test-cell tooling and die handling are crucial for efficient strategies. A "shift-to-left" approach assesses device reliability early, preventing underperforming die from use in multichip modules. Developing universal device carriers to accommodate variable sizes and access points requires expertise in materials and collaborative innovation. Leading IDMs and foundries must validate semiconductor IP before advanced packaging integration. After integration, additional testing is necessary to meet consumer demands for performance and reliability.  This presentation covers innovations in cleaning materials and device carriers that support reliable handling and cost-effective testing.

クロージングのご挨拶

Nobuhiro Kawamata, VP & Country Manager, FormFactor Inc.

代表取締役　川又　信尋

レセプション