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Mike Slessor, President & CEO - FormFactor Inc.

Dr. Deepak Kulkarni, Fellow, Advanced Packaging, AMD

Chiplet architectures are fundamental to the continued economic viable growth of power efficient computing. Thus, the criticality of advanced packaging technologies and architectures correlated to Moore’s Law’s next frontier is high. New heterogeneous architectures, along with AMD’s industry leading advanced packaging roadmap, enable power, performance, area, and cost (PPAC). PPAC considerations per product influence the choice of Substrate (2D), Fanout based (2.5D) and Hybrid Bonded (3D) technologies and will be addressed in this keynote. Finally, AMD’s High Performance Fanout previewed in the RDNA3 architecture along with enabling technologies like power delivery and thermal improvements will be detailed.

Daniel Bock, Sr. Staff Applications Engineer, FormFactor Inc.

The growth in AI (such as ChatGPT and BING AI) is requiring large investments into the expansion of data centers, driving higher and higher data rates in IO devices.  In order to reach these data rates, wafer test is moving to bandwidth > 60 GHz.  Pyramid Probes are widely used for wafer test at up to 81 GHz and in high volume manufacturing (HVM).  These probes feature micro-strip or CPW transmission lines that provide controlled impedance and low loss (<6 dB at 67 GHz) for the industry leading performance at wafer test.  However, in the standard layout, the signal trace faces the wafer and is only 70 um away, so that it can sometimes couple to structures on the wafer.  This coupling can have significant effects in some cases, in both DUT performance and RF calibration of the probe head.  Further, one expects the coupling to increase as the probe ages and the tips become shorter, bringing the microstrip closer to the wafer.  To reduce this coupling, Pyramid Probes using a microstrip with the ground between the transmission line and the wafer (inverted microstrip) are available.  In this study, we will use probes with standard and inverted microstrips to measure TIA (transimpedance amplifier) performance.  Measurements before and after aging the probes will be compared to characterize these effects.  In addition, we will look at different calibration methods (SOLR, SOLT, SOL de-embed) and compare them to provide recommendations for calibration.

John Muir, Director, Applications Engineering, FormFactor, Inc.
David Cooke, Product Marketing Manager, FormFactor, Inc.

The need for high bandwidth computing has driven the development of 3D Heterogenous modules, these vertically stacked memory packages for High Bandwidth Memory have many benefits over traditional modules, lower power consumption, significantly higher memory storage, higher performance coupled with smaller and smaller footprints. 

Advanced packaging IC revenues continue to grow year on year. The advent of this technology has created the need for known good die test of the TSV connected memory stacks to reduce risk and cost.  Early test data on the stack yield after manufacturing is essential to control final costs.  FormFactor probe solutions provide the necessary test medium for aluminum pads for sort and functional speed test using FFI’s T11 family of probes and copper bumps with vertical MEMs MF family.

In this presentation we will explore how we engage in this market.

Simon Reissmann, Sr. Principal Applications Engineer, FormFactor, Inc.

In this talk we will discuss FormFactor’s industry leading silicon photonics coupling technology, Pharos, for edge coupling in V grooves and lowest loss coupling on grating couplers. Further we will cover the new four mouse-click automated calibration routine released in the latest silicon photonics software solution suite.   

FormFactor’s SiPh solution includes a built-in power measuring function that quantifies the laser output coming directly from one of the Pharos fiber channels. This allows the user the flexibility to move from measurements directly on the wafer to an aux site and verify the laser power coming out of the probes, automatically position  one of the eight channels of the probes, and to go back to the last die or subdie measured to proceed. All that is accomplished by sending one integrated command,  without the need to manually navigate to the right spot on the aux site, position the probe in the correct location, and so on. This eliminates user miscues completely and is a great timesaver.

Also, with a four mouse-click automated calibration, manual errors are eliminated. This automated routine assures consistent and repeatable calibration results without missing a step, and saves significant time.

Brandon Boiko, Sr. Applications Engineer, FormFactor Inc.

Many emerging technologies in Quantum and High-Performance Computing industries rely on the use of superconducting materials and their unique properties. Components like SNSPDs and SQUIDs use common superconductors like Nb and Al for their convenient transition temperatures of ~10K and ~1K respectively. Development of new exotic superconductors with better performance and manufacturability is an ongoing area of research.  This talk will discuss the general measurement methodologies and best practices for characterizing the transition temperature for superconducting materials.

David Raschko, Director, Product Marketing, FormFactor, Inc.

Datacenters and High-Performance-Compute (HPC) applications are quickly approaching and even exceeding 1kW of total power in a single chip in normal operating conditions. In addition to new applications, the transition to new nodes further increases the total power per unit area in a semiconductor, which compounds the challenge of increased power and thermal output of a device during test in even low-power consumption applications such as mobile application processors. This continuous increase in device output power creates several challenges regarding wafer test, particularly with maintaining contactor integrity at high current and in high-temperature environments. To combat this trend, higher CCC in the probe during test must advance in a rate similar to the increased power being observed in the DUT leading to increased uptimes and lower cost of test. This paper will address several techniques that can be utilized in the probe card to maximize CCC to achieve an effective CCC of >2.5A in a probe card at a 80um minimum pitch including both new probe developments along with architectural improvements to maintain probe integrity in a high-stress, high-current environment.

Pranav Shrivastava, Principal Applications Engineer, FormFactor Inc.

F_t and F_max are important figure of merits for RFCMOS transistors, and it has been a huge challenge in the industry to characterize and get reliable F_max measurements. Accurate, repeatable and traceable wafer-level F_t and F_max measurements are critical for circuit designers prior to RFIC design work, and are needed to support the emerging high data rate, low latency wireless applications such as beyond 5G, wireless multimedia, IOT, big data and vehicular positioning systems.

The presented work investigates the impacts of how RF probe contact resistance on test pads of calibration standards and devices affect the F_t and F_max measurements of RFCMOS transistors. It is found that poor probe contact on calibration standards lead to large extracted load standard inductance when eLRRM calibration is used, degrading transistor F_max.  In this talk, a new RF wafer test strategy is proposed to help device and test engineers obtain accurate, repeatable, and traceable F_t and F_max measurements.

Jack De Grave, Director of Business Development, FormFactor Inc.

New quantum technologies such as quantum communications, sensing, and computing hold the promise of revolutionizing digital security, finance, logistics, pharmaceuticals, and more over the next two decades. Advancing quantum technologies requires new test and measurement strategies that provide reliable methods of testing superconducting and integrated photonic devices below their transition temperatures (typically less than 4K).

This talk will discuss FormFactor’s photonics application layer that includes an automated fiber array scan and alignment function to streamline test in cryogenic conditions. This technology has been coupled to a new cooling system to bring automated test and measurement to a sub-2K environment. Here, we show the photonic application layer on the our newest solution, the IQ2000 rapid chip-scale tester, and share early results.

Dr. Choon Beng Sia, Test Technologist, FormFactor Inc.

 The semiconductor industry continues to see the relentless downscaling of gate length and development of new architectures for silicon-based transistor to 2 nm and beyond. The on-state currents of such advanced transistors are increasing with decreasing supply voltages. Their off-state currents are kept very low to reduce power consumption. Smaller test pads to reduce lithography costs and the use of copper backend metallization have increased the difficulties for probes to have low and stable contact resistance as there are little fresh pad metal available for deeper probe scrubs or re-probing. These issues aggravate especially at elevated temperatures when the pad aluminium cap layers have been probed and their underlying copper metallization oxidise rapidly, hindering the ability to achieve good probe contacts. In this talk, we introduce the next generation advanced guarded DC probes with small probe scrubs, low leakage performance and true Kelvin force sense probe tips to address the test challenges of making precise and consistent device modelling wafer measurements.

Join us after the event for some networking.