Mike Slessor, President and CEO, FormFactor Inc.
Michael D. Slessor has served as our Chief Executive Officer of FormFactor, Inc. since December 2014, and as a Director since October 2013. Mike served as President from October 2013 to December 27, 2014, and as Senior Vice President and General Manager, MicroProbe Product Group from October 2012 to October 2013. Before joining FormFactor, he was President and Chief Executive Officer of MicroProbe from July 2008 through the October 2012 closing of FormFactor’s acquisition of MicroProbe. Prior to joining MicroProbe, he held various management, product-marketing, and applications-engineering positions in the semiconductor industry, primarily with KLA.
Mike received his Ph.D. in Aeronautics and Physics from the California Institute of Technology and his B.A.Sc. in Engineering Physics from the University of British Columbia.
Keynote: Semiconductor Industry: beachheads that drive the innovation
Semiconductor wafer suppliers and more generally other upstream semiconductor material providers continue to enjoy strong demand from chipmakers. However, with an expected demand that should weaken, what are we facing in the next couple of years? Upcoming challenges are numerous but innovation is still predominant. When touching at the realm of innovative technologies in areas such as 5G, future of computing, or silicon carbide, advanced packaging or silicon photonics, let’s review the most innovative areas of the semiconductor industry.
Guillaume Girardin, Chief Technology Officer, Yole Intelligence, part of Yole Group
Guillaume Girardin is Chief Technology Officer at Yole Intelligence, part of Yole Group.
Guillaume’s mission is to ensure the quality, consistency, and evolution of Yole Intelligence’s products and services related to the semiconductor industry. He holds a Ph.D. In Physics and Nanotechnology from the Claude Bernard University Lyon 1 (Lyon, France) and an M.Sc. in Technology and Innovation Management from EM Lyon School of Business (Lyon, France).
5G mmWave: Multi-site RF Probe Cards Enable Lower Cost-of-test in Mass Production
5G mmWave systems are here. Advanced Antenna-in-Package modules and RFFE chipsets are integral to the latest generation of high-end smartphones and tablets, and this capability is becoming more ubiquitous in 2022. These chips, containing a massive amount of mmW content, are ramping in mass production, and the companies producing them need a way to reduce cost of RF test. Our collective challenge spans multiple organizations requiring concerted coordination between sub-systems and immaculate preservation of impedance. Additionally, direct measurement test time is appreciable for advanced-RF devices, which drives the need for more parallel measurement insertions. One converging approach, is the use of RF switching on PCB to expand available tester channels and support multi-site probe heads through sequential-parallel testing. To realize actual cost reduction, tester and probe card companies need to evolve quickly to support increased parallelism of mmWave testing.
This session drills down into the RF test cell to examine enhancements enabling increased parallelism using new probe head architectures. The development efforts began by enlarging the active probing area using an advanced membrane process. This new capability created a canvas for RF engineers to develop a host of transmission line structures aimed at high density RF routing from the die to the PCB. Innovation continued - with several loopback options, and a host of new structures to support densification. Another problem uniquely solved with the new membrane, is the ability to support 50 Ohm and non-50 Ohm transmission lines simultaneously to match the impedance needs of the tester and overall performance expectations. We'll share examples and typical S-parameter performance for several line types during this session.
In closing, this collection of new probe head elements is enabling test engineers to configure their high-volume RF test solutions in novel ways, and we are eager to equip the industry with new test possibilities.
Ryan Garrison, Senior Product Business Manager, Probes Business Unit, FormFactor Inc.
Ryan Garrison is a Senior Product Business Manager with FormFactor’s Probes BU focused on RF probing solutions. With nearly 20 years at FormFactor, he has held multiple engineering and leadership roles in operations and the development of Analytical RF Probes, Probe Stations, and now Production RF Probes. His current responsibility centers on the business of expanding RF test parallelism for sub-6 GHz and mmW antenna devices. Most recently Ryan lead a team through the development-process-to-product-release of a new probe head effectively doubling the parallelism of RF test using FormFactor’s membrane technology. Prior to joining FormFactor, Ryan graduated from the Oregon State University in Industrial and Manufacturing Engineering.
Matching Module Loss in the Probe Card for Digital Test During Wafer Sort
As digital speeds continue to double every 2 to 3 years, novel methods for countering loss will become increasingly prevalent. These loss-countering methods, typically called equalization, also need to be tested during wafer sort. To enable full-functional testing, probe cards will need to be capable of matching the expected loss profile of the module where the die will be operational. This will drive increasing complexity in the probe card and will require new probe card features that this paper will address. Included in this paper are a description of the upcoming equalization challenges, how system loss can be matched in a probe card, and how wafer sort is going to adapt to the increasingly fast speeds seen in digital communication protocols.
Daniel Bock, RF Applications Engineer, FormFactor Inc.
Daniel Bock got his Ph.D. in Physics at Carnegie Mellon University in 2006, working on Superconducting Nanowire Bolometers in the NanoFabrication Lab. He then went to work in 2007 with Physical Optics Corporation in Torrance, CA. There, he was awarded more than $4M in SBIR research grants from the Department of Defense, developing innovative high power tunable filters for use in Electronics Warfare and Electronics Attack systems. He joined the Cascade Microtech Business Unit in June of 2012. Since joining, he has been working to extend the mmWave bandwidth of Pyramid Probe technology, including RF test of automotive radar devices. He has also led the development of the Custom Calibration Substrate (Custom ISS) product line to supplement the standard ISS line.
FRT Metrology for Advanced Packaging
In Advanced Packaging new technologies were developed to achieve devices with high density in a small space, ultimately leading to "hybrid bonding" with even the highest density so far, which enables a higher bandwidth and an increased power. Currently, micro bumps and hybrid bonding are coexistent, as hybrid bonding is not required in all areas. In this regard, the need for flexibility in wafer metrology has just exploded in the past, and with new technologies and processes, it seems to keep growing even further and even faster.
FRT’s MicroProf® AP tool is specifically designed for metrology of Advanced Packaging applications. The tool measures and handles numerous wafer types up to 12” for front- and back-end, at different 3D packaging process steps, as well as glass, lens and non-SEMI standard wafers, wafers on tape in frame. With our SurfaceSense™ multi-sensor technology, the modular based software and retrofittable sensor hardware, we create the flexibility that customers need in heterogeneous production cycles.
- FRT Metrology solutions in Advanced Packaging
- High-precision micron-level process control of RDLs
- CMP die and wafer flatness evaluation for planarization and hybrid bonding
Dr. Juergen Koglin, Director Applications Engineering, FormFactor Inc.
Juergen Koglin has been engaged in surface metrology since his diploma thesis in physics at the University of Bonn. During his doctoral thesis on optical near-field microscopy at the University of Muenster, he remained with surface metrology, and continued his research as a postdoctoral scientist after receiving his doctorate in 1996. More than 20 years ago, he joined FRT as the head of the applications department. Since FRT became part of Formfactor in 2019, he now serves as Director Applications Engineering for FRT Metrology.
High Throughput SiC Metrology and Inspection
Microchips made of silicon carbide (SiC) are currently driving a technological leap forward in electromobility and will in future set the pace in power electronics - the control center of electric and hybrid vehicles. Compared to the silicon chips used to date, SiC semiconductors show a better electrical conductivity. On one hand, this enables higher switching frequencies and, on the other hand, it ensures that significantly less energy is dissipated in the form of heat. The more efficiently the power electronics work, the more energy is available which leads to an increased range of the vehicle. The significantly lower heat losses of the chips and the fact that they also can operate at much higher temperatures allow for a reduction of costly cooling components. This in turn has a positive effect on the weight and overall costs of electric vehicles.
In a market where competition is so intense, economic success depends above all on product quality. Thus, process tolerances must be continuously monitored during production. Manufacturers rely on our high-quality, multi-sensor metrology and inspection technology for this job. With our innovative solutions, we help to maintain the very high quality standards required.
In process monitoring and quality control, there are a number of parameters for characterizing wafer topography and thickness. These include TTV (total thickness variation), bow, warp, flatness, roughness, waviness and layer thickness determination of thin films, or layer stacks. It is also necessary to perform automated measurements with high throughput rates. For this purpose, automatic handling of the samples is required. FRT Metrology has decades of expertise in fully automated silicon and sapphire wafer metrology and inspection, which can be applied equally to silicon carbide. FRT MicroProf® MHU was developed specially for these requirements and can be easily configured for different SiC wafer types and applications.
Egidio Carria, Staff Process Engineer, STMicroeletronics
Egidio Carria is a staff process engineer at STMicroeletronics. After finishing his Ph.D. in Physics and post-doctoral work at RWTH University, he has been employed with STMicroelectronics as a process engineer in ADG R&D group in Catania. In 2018 Egidio moved to the FEM organization as a process engineer in high volume Silicon epitaxy fabrication, taking care of the robustness project within this organization. In 2020 he moved to Norrkoping after the acquisition of Norstel by STM where he contributed to the industrialization program for metrology and defectivity areas. In 2022 he moved back to Catania to manage the start up and ramp up of the new 8” SiC epitaxy fab with the role of project manager within the engineering group.
Bastian Troger, Senior Manager of Marketing at FormFactor FRT Metrology
As a graduate engineer specializing in physical optics, Bastian Troeger can look back on many years of professional experience in the area of optical metrology. His career at FRT started in 2007 in the development department, followed by the establishment of a new product management department and eventually led him to the management level of FormFactor FRT Metrology.
Quantum/CryoCMOS: Enabling the Future of Computing
Quantum computing development is accelerating and showing promise to commercialize in the next years however key challenges must be addressed in the fabrication and test of superconducting devices used for this purpose.
Superconducting or spin qubit devices go through complicated fabrication processes involving multiple additive and subtractive steps. As well, prior to characterization, time consuming and expensive techniques such as wire bonding and packaging are required.
Low performance devices and defective qubits lead to wasted time and money on unnecessary equipment cooldowns on deployment systems and slow down critical feedback for new fabrication processes. Pre-characterization measurements on quantum processors can establish resonator quality and qubit yield prior to the dilution refrigerator cooldown that can prevent this wasted time and money on cooling down poor devices.
The test and measurement temperature is typically close to absolute zero, in the range of 4K to sub-50mK, for quantum qubit device characterization.
This presentation will discuss these challenges and present use-cases from mK up to 77K chip scale probing as well as wafer scale probing; all of which can incorporate Formfactor's probe interface technology.
Dong-Thuc Knobbe, Sr. Staff Business Development
Dong-Thuc Knobbe started her career as a Lab Engineer for Bio-Medical Engineering at the Research Center FZ-Juelich in Germany. In 2004 she began work with Formfactor as a Product Engineer working on customizations throughout the probe station portfolio. She is responsible for key customer projects for both the custom products group and cryogenic & vacuum stations. Ms. Knobbe is currently focused on cryogenic products at FormFactor as part of the HPD Cryogenic Product Group, strengthening the Quantum Computing application and supporting customers to get quantum computing devices characterized.
Fully Automated Integrated Silicon Photonic Wafer Test
Integrated silicon photonics has found extensive use in modern high speed optical links. These optical transceivers are composed of various structures which require extensive passive, DC, RF, and electro-optic characterization at wafer level. A high degree of automation in addition to minimal reconfiguration of the test setup is necessary to improve test throughput. Herein we discuss the use of the CM300 silicon photonics probe station to enable automated full wafer characterization of various passives, DC electro-optic, and VNA measurements of thermal phase shifters, modulators and photodetectors.
Golam Bappi, Senior Photonic Test Engineer, Ayar Labs
Golam is a Senior Photonic Test Engineer at Ayar Labs. He is responsible for wafer level electronic and photonic characterization of components that form the optical transceiver macros in high bandwidth TeraPHY optical I/O chiplets, and planar lightwave circuits for the SuperNOVA laser source. His current work focuses on developing efficient wafer test solutions using high pin count probe cards for the CM300 which enable complete optoelectronic test for determining known good die. Golam graduated from the University of Toronto in 2020 with a PhD degree in Electrical Engineering.