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COMPASS 2019 - Hsinchu, Taiwan - May 24, 2019

Upcoming Event: Munich, Germany - November 2019

Hsinchu-Taiwan

COMPASS 2019 - Hsinchu, Taiwan

FormFactor’s users’ conference, COMPASS comes to Hsinchu, Taiwan on May 24, 2019. At the event, speakers will share test insights on a wide variety of emerging applications, such as 5G, silicon photonics and high-power devices. Attendees will learn practical tips on how to improve test accuracy and efficiency. In addition to technical sessions, attendees COMPASS participate in networking opportunities to discuss creating the future of the connected world!

When: Friday, May 24th – 10:00 – 15:00
Where: GIS HSP Convention Center, 4nd Floor (Room 403) Hsinchu Science Park
Cost: FREE

COMPASS 2019 - Taiwan Agenda

Click the links below to see presentation abstracts and speakers

09:15 - 10:00   Registration

Registration and pre-event networking

10:00 - 10:15   Welcome and Introduction

Amy Leong

Amy Leong, Chief Marketing Officer and Senior Vice President, Mergers and Acquisitions

Amy Leong has been with FormFactor since October 2012. Prior to this, Amy was the VP of Marketing at MicroProbe from April 2010 through the October 2012 closing of FormFactor’s acquisition of MicroProbe. Before joining MicroProbe, Ms. Leong worked at Gartner, Inc. as a Research Director from 2008 to 2010 and covered the ASSP system-on-chip and microcontroller markets. From 2003 to 2008, Ms. Leong worked at FormFactor where she served as Senior Director of Corporate Strategic Marketing and Director of DRAM Product Marketing. Prior to FormFactor, Ms. Leong worked in a variety of semiconductor process engineering and product marketing roles at KLA-Tencor and IBM.

Ms. Leong holds an M.S. in Material Science and Engineering from Stanford University and a B.S. in Chemical Engineering from the University of California, Berkeley

10:20 - 10:50   5G Wafer Test and the New Age of Parallelism

5G Wafer Test and the New Age of Parallelism

The development of new RF devices (5G and high-speed digital components) is changing the landscape for RF probing.  For many years, RF probing in frequencies beyond cell phone and WiFi frequencies was a niche area, only requiring a very small number of lines as well as not meeting the needs for High Volume Manufacturing (HVM).  5G is leading the way to both higher RF frequencies with the added 28, 38, and 60 GHz bands, as well as the needed improvements in infrastructure with high speed digital devices for data backhaul through the fiber network because of the expected large increase in data needs.  The race to meet higher bandwidth for infrastructure development is leading to a new set of requirements because of the increase in channels and volume.  Because of this, the requirement for more parallelism at high speeds is leading to new probe card architecture.  This includes: frequency improvements of vertical MEMS type probe heads, and membrane probe cards with PCB active circuitry to increase the channel density.  In addition, to meet the high standards for signal integrity at these high speeds, the relative repeatability of RF measurements per touchdown, RF calibration performance, and probe head inductance comparisons will be reported in order to provide a path for probing technology selection based on the end use requirements.

10:55 - 11:25   Autonomous RF/mmW Measurement and Calibration to Accelerate 5G Time-to-Data

Autonomous RF/mmW Measurement and Calibration to Accelerate 5G Time-to-Data

RF device over temperature characteristics are generally required for all accurate semiconductor device models. During temperature transitions the RF characteristics of the probes and cables vary, and need recalibration at different temperatures. Calibration is done typically with ambient temperature substrates, and the probes can cool during calibration affecting accuracy, so very fast work is required. This requires highly skilled users that can operate wafer probers quickly, and frequently attend to the prober during a test sequence. To address this issue, we developed our Autonomous RF measurement assistant. The Autonomous RF measurement assistant is a complete system that fully automates the process of over temperature RF testing. In this presentation, we show the methodologies used to qualify operation. Videos of actual operation and some scripting will be shown to highlight how simple the tool is to use.

Hank-Chiang

Hank Chiang, Sr. Applications Engineer, Application Eng, FormFactor Taiwan

Hank Chiang joined FormFactor from 2018 as Sr. Applications Engineer. Currently he is based in Taiwan and focuses on WInCal support, Silicon Photonics and high-power applications. Prior to FormFactor, Hank worked at Keithley Instruments for 11 Years and served as Customer Service Manager. At that time, he was recognized twice with Keithley’s QSII (Quality-Service-Innovation-Integrity) award for PIV application and his role in developing business with Foxconn. In addition, he has abundant experience and knowledge in DC IV/CV, Flash, WAT, TEG, Wireless applications. After Keithley, Hank worked for seven years at STAr technology as Director of the Engineering Department.  During his career at STAr, he helped to build up the service and application teams to support WLR, PLR and Keysight B1505 high-power solutions.

11:30 - 11:55   Silicon Photonics - Challenges and Solutions for Wafer-Level Production Tests

Silicon Photonics – Challenges and Solutions for Wafer-Level Production Tests

Data centers around the world currently consume about 7% of the earth’s total power output. To satisfy the increasing demands for cloud computing and services for various new emerging applications such as artificial intelligence, genomics revolution, data analytics and video transcoding etc, hyperscale data centers are being built around the world at an accelerated pace, with analyst predicting up to 20% of earth's total power output consumed by data centers in 2025. Optical fiber communications within data centers and the use of Silicon Photonics (SiPh) to implement these optical transceivers present a very attractive option, drastically reducing power consumption, cost and size of these transceiver modules. In addition, the mature silicon CMOS processing technologies and advanced packaging technologies both offer an established production solution to fabricate such silicon-based optical transceiver modules. For effective heterogeneous integration and packaging of these silicon-based optical transceivers, all individual functional dies, for example, logic, photonics and continuous wave laser etc. must each be tested prior to stacking and packaging. One of the key challenges for wafer-level photonics tests and measurements is the need for full test automation to satisfy the high throughput requirements for these known-good-die tests - especially tedious when test engineers need to work with optical, DC, RF probes to handle unlimited permutations of possible test structure layouts at the same time. Another challenge is optimizing test time as optical and opto-electrical tests require long measurement time due to complexity of the fiber alignment/coupling procedure and fine sweeping steps needed during measurements.  Finally, the ability to accurately test the final product is another big obstacle since most SiPh chips utilize edge coupler to transfer light in and out of the chip after packaging while majority of the commercially available wafer-level test solutions require grating couplers for wafer top-side light transfer. In this paper, proposed solutions to these challenges will be discussed, including layout rules and standardization for the ease of automation implementation, utilization of fiber array for parallel testing and optimization of input light for higher precision gauging and correlations with the final product performance..

ChoonBeng-Sia

Choon Beng Sia, Customer Applications and Production Solutions (CAPS) Group, FormFactor

Dr. Choon Beng Sia is a Nanyang Research Scholar and has received B.E., M.E. and Ph.D. degrees from Nanyang Technological University, Singapore. He is a member of the FormFactor Customer Applications and Production Solutions (CAPS) team, responsible for developing solutions for emerging wafer-level measurement applications. Dr. Sia was recently elevated to a Senior IEEE member and serves on the IEEE MTT-11 Technical Committee focusing on developing standards and best practices for microwave measurements. He also represents Singapore as a technical expert on the IEC TC47 technical committee. Dr. Sia holds nine international patents with two pending and has more than 200 citations referenced to his technical publications.

12:00 - 13:00   Lunch and Lucky Draw

13:15 - 13:40   New Test Flows for 2.5D/3D Advanced Packaging and “Known-Good-Stack” Verification of Singulated HBM2

New Test Flows for 2.5D/3D Advanced Packaging and “Known-Good-Stack” Verification of Singulated HBM2

High-Bandwidth-Memory continues to evolve and demand more stringent testing requirement in terms of test coverage & speed as well as probing accuracy. The recent breakthrough of 2.5D and 3D wafer level packaging technologies has opened up many new possibilities and challenges from test perspectives. A faster tester with higher signal fidelity performance is needed along with an advance probe card technology that can provide the required signal fidelity and the ability to successfully probe on TSV micro-bump structure in an ultra-low pitch grid array. The new test flows and test insertion points needed to validate true “known-good-stack” will be discussed.

This presentation introduces the HBM2 requirements and addresses the key electrical challenges focusing on simulation versus actual tester measured results collected from direct MicroBump probing above 2 Gbps on all HBM2 Direct Access data channels.

In addition, challenges of wafer level sort will be discussed in term of thermal expansion responses of the various HBM2 stack configurations.

Alan-Liao

Alan Liao, Director Product Marketing, FormFactor

Alan Liao has been with FormFactor since August 2008. Alan was an electrical design engineer at FormFactor and designed our first 300mm full wafer contact probe card for SmartPhone DRAM wafer sort testing. As an electrical R&D engineer, Alan helped to continuously improve and develop probe card technology to meet advanced memory testing requirements. In 2012, Alan moved to a customer design engineer position to be the technical interface with our key North America DRAM customer. During 2014, Alan joined Product Marketing as SoC Product Manager to oversee the China and Taiwan Region. In 2019, Alan was promoted to Director of Probe BU product marketing.

13:45 - 14:10   Overcoming the Wafer Test Challenges of Advanced Power Semiconductor Devices (GaN, SiC, Si)

Overcoming the Wafer Test Challenges of Advanced Power Semiconductor Devices (GaN, SiC, Si)

Greater demand for energy efficiency in systems, cars, consumer appliances, portable electronics, and new connections to the Internet of Things, are continuing to drive the advancement of power semiconductor devices, with year on year record-high level demand. As a result, companies and foundries around the world are increasing test capacity in R&D, high-performance device production and general high-volume manufacturing. Next generation power devices are rapidly being developed to bring down end-user device costs and support a wide range of growing application performance needs. A key challenge engineers face is testing on-wafer instead of in-package.

In this presentation, you will learn the following:

  • System requirements for on wafer high voltage and high current measurements
  • Typical devices and substrate materials
  • Addressing high power test challenges
    • Anti-arcing for high voltages
    • Low contact resistance of probe to device
    • Low contact / thermal resistance, with uniformity between wafer and chuck
    • Accurate device models for circuit designers (correlation of package to wafer)
  • Wafer level testing with safety built into the system
peter-andrews

Peter Andrews, Director, DC Market Segment, FormFactor

Peter Andrews started his technology career in Melbourne Australia as a computer operator / technician. After receiving his BS Computer Science (RMIT Australia / Lewis & Clark Portland OR), Peter started at Cascade Microtech in 1988 developing test executive measurement software for Agilent/Wiltron/Keithley instruments. Later, he helped develop Cascade’s first integrated measurement system for Noise Parameter/S-Parameter test, and RF/uW VNA Calibration software. Shifting to direct customer application support, Peter spent 4 years in Europe as Senior Applications Engineer, and back in the US, concentrated on development of Cascade’s probe stations / measurement systems as Senior Product Marketing Manager for 12 years. He holds multiple technology patents and product industry awards in test and measurement. In technical management he was Director of Sales and Support (Americas), and is currently Director Marketing, DC Segment, for the Systems Business Unit at Formfactor, focusing on DC, low noise, and high power applications.

14:15 - 14:40   Hybrid MEMS Probe Technology for Advanced Mobile and High-Performance-Computing Applications

Hybrid MEMS Probe Technology for Advanced Mobile and High-Performance-Computing Applications

Less than two years ago, Qualcomm and FormFactor introduced the innovative Hybrid MEMS probe technology for advanced probing applications.  Hybrid MEMS technology allows multiple probe designs to be used in a single probe head design, with each probe design optimized for a specific purpose.  The technical innovation to enable hybrid design is to leverage multi-layer composite MEMS fabrication technology, which allows the optimal wafer test performance by including otherwise mutually exclusive requirements such as fine-pitch and high current carrying capability.

One challenge to overcome was a potential non-uniform probe tip wear rate due to cleaning and a non-uniform bump indentation due to different probe cross-section. Over the last year, FormFactor has optimized a family of hybrid MEMS probes with pitch range from 80um to 130um.   These probes have demonstrated comparable wear rate and probe mark size/depth when used in a single probe head.  Qualcomm have implemented several designs in production environments at its foundries for both mobile application processors. In this paper, we will update our latest production experience and results of hybrid MEMS probe designs, as well some interesting unexpected findings for future improvement opportunities.

Amy Leong

Amy Leong, Chief Marketing Officer and Senior Vice President, Mergers and Acquisitions

Amy Leong has been with FormFactor since October 2012. Prior to this, Amy was the VP of Marketing at MicroProbe from April 2010 through the October 2012 closing of FormFactor’s acquisition of MicroProbe. Before joining MicroProbe, Ms. Leong worked at Gartner, Inc. as a Research Director from 2008 to 2010 and covered the ASSP system-on-chip and microcontroller markets. From 2003 to 2008, Ms. Leong worked at FormFactor where she served as Senior Director of Corporate Strategic Marketing and Director of DRAM Product Marketing. Prior to FormFactor, Ms. Leong worked in a variety of semiconductor process engineering and product marketing roles at KLA-Tencor and IBM.

Ms. Leong holds an M.S. in Material Science and Engineering from Stanford University and a B.S. in Chemical Engineering from the University of California, Berkeley

14:45               Reception and Lucky Draw

COMPASS 2019 - Taiwan Registration

When: Friday, May 24th – 10:00 – 15:00
Where: GIS HSP Convention Center, 4nd Floor (Room 403) Hsinchu Science Park
Cost: FREE

COMPASS 2019 - Taiwan

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