Bart De Wachter, Test Engineer, imec

Bart De Wachter joined imec, a leading international research center in nanoelectronics, in 1999 from Tractebel, a global engineering consultancy company. He holds a degree in Electrical Engineering from Odisee (Ghent, Belgium). Bart is excited to be a part of the imec environment, where there are always new R&D paths to explore and new connections to make. He served as a chip design and layout engineer, and now focuses on automated semiconductor wafer-level testing and related operations in imec's state-of-the-art wafer fab. He aspires to design in-fab semiconductor parametric/functional test solutions which perform a wide variety of electrical tests in the most accurate and fast way, handling high wafer test throughputs (24/7 automation) in support of imec's stacked 3D-IC and CMOS Logic nanometer R&D activities. He works closely with industrial partners from around the world.

The CM300, MHU300 and PDC50 in the Wafer Fab

To handle high volumes of wafer probe and test,  it required a probe station equipped with a wafer cassette load port/wafer handler to allow a 24/7 unattended test modus (non-stop wafer load and test). The CM300 probe station was selected, expanded with the MHU300 wafer handling unit and a PDC50 customized probe card solution for low-resistance (<1 Ω) probe-to-wafer contacts, low-leakage levels (<pA) and tiny probe-pad scrub marks which are favored for downstream processing.